As the semiconductor industry has developed data processing systems which provide increased functionality at faster speeds, a key component for implementing these systems has been a memory for storing programs and applications needed by the system. With increased demands for faster data processing systems, comes increasing demands for larger and faster memories which store more applications and deliver that program information more quickly. In turn, with increasing demands for larger and faster memories, a die size and the manufacturing costs associated with developing the memory must be maintained. These constraints have driven designers of memories to push the technological limits of feature size reductions with any conceivable process enhancement. However, as feature sizes continue to decrease within the two-dimensional planar surface of a silicon substrate, electrical effects such as line-to-line capacitive coupling become more dominant and, eventually consume much of the performance enhancements sought by the reduced feature sizes. Therefore, a challenge in current memory development is to improve the relationships between design parameters and process results to better utilize the limited resources of a silicon substrate for transistor structures and to exploit the vertical topology for all other non-device structures.
In implementing a memory in past data processing systems, a memory cell such as that illustrated in FIG. 1 was typically utilized. In memory cell 100 of FIG. 1, six transistors perform the functions of a single port SRAM cell. Memory cell 100 comprises four n-type transistors 102, 106, 110, and 112, and two p-channel devices 104 and 108. Transistors 104-110 create a cross-coupled memory latch which is used to store data. Transistors 102 and 112 are transfer devices which provide access into and out of the latch under control of a word line signal. In a memory configuration, many memory cells are common to each bitline pair, complement bitline and true bitline. Furthermore, it is the function of transfer devices 102 and 112 to provide an open pathway between the cross-coupled memory latch and the external environment for the performance of "read" operations and "write" operations.
While FIG. 1 illustrates a typical implementation of a single port static memory cell, FIG. 2 illustrates a two-port static memory cell 200. In a dual port memory cell, such as memory cell 200, two separate paths are provided to read and write the same four device cross-coupled memory latch described in single port SRAM cell 100 in FIG. 1. A first transfer path is defined by transistors 202 and 214 which are coupled to bitlines in a wordline corresponding to port 1. Similarly, transistors 204 and 216 provide a second transfer path corresponding to a second port of the dual port memory cell 200. The additional transfer devices are implemented to execute a second and separate read and write to memory cell 200. Furthermore, in order to maintain each port's unique identity, an additional pair of bitlines is also required. In the more traditional two-port memory cell layouts, such as that illustrated in FIG. 2, the second pair of bitlines are placed adjacent to and in the same wiring plane as the first pair of bitlines. This placement requires more surface area to implement and, therefore, increases the overhead associated with implementing such dual-port memory cells. To minimize silicon surface area, these bitlines are often placed as close together as the manufacturing process will allow. These parallel bitlines typically have lengths ranging from 64 to 512 cells in height. Additionally, these parallel bitlines become very sensitive to transitions on neighboring bitlines.
The sensitivity is a result of increased bitline-to-bitline capacitance. Increased bitline-to-bitline capacitance from traditional layouts and implementations of dual-port memories reduces the effectiveness of differential bitline sensing, a technique which is common place in memory designs. In such differential bitline sensing, a small amount of differential offset developed between bitline pairs during a read operation is detected. For example, when a transfer device, such as transistors 202, 204, 214, and 216 is enabled, a portion of the memory cell begins to discharge one of the two precharged differential bitline pairs, wherein the differential bitline pairs are precharged to a first reference voltage Vdd. An offset between true and complement bitlines continues to increase, until the differential between the bitline pairs is sufficient to be detected reliability by a differential amplifier, commonly referred to as a sense amplifier in the data processing area. During this discharge and sensing step, line-to-line coupling detracts from the differential offset development by transferring charge from one bitline to another. As a result, discharge of the differential bitlines must continue to consume more cycle time to compensate for the charge transfer or loss between the reference bitline and an active (pulldown) bitline.
Several techniques have been implemented to manufacture dual-port memory cells with higher density. One such implementation is disclosed in U.S. Pat. No. 5,292,678 by Dhong, et al., and assigned to International Business Machines Corporation. In U.S. Pat. No. 5,292,678, a folded bitline architecture is used to implement a high density memory layout, including DRAMs. In this type of folded bitline architecture, bit pairs are manufactured to be vertically aligned with one another, and are typically separated by a passivation or other resistive layer during a processing step. The folded bitline approach attempts to use two metal layers for manufacturing purposes within one horizontal wiring plane by using some special processing steps. These special processing steps are often expensive and are difficult to manufacture.
Therefore, a need exists for a dual-port memory cell having configuration and layout which provides for greater density and reduces an amount of cross-coupling among elements of the memory cell while using standard manufacturing processes.